This invention relates generally to dynamic random access memories (hereinafter referred to as "dRAM"), and more particularly to a structure which is suitable for obtaining large capacitance by use of a very small memory cell. This invention relates further to a trench capacitor formed in a semiconductor and to a method suitable for fabricating a very small capacitor.
As disclosed in Japanese Patent Laid-Open No. 154256/1983, a conventional trench capacitor is formed by first forming a n.sup.+ -layer on a substrate and then isolating this n.sup.+ -layer by a trench to obtain individual capacitors. If this trench is used for the purpose of device isolation, too, the n.sup.+ -layer must not be formed at part of the trench, that is, in a region in which an MOS transistor is to be formed. In other words, one trench must be devided into a region in which the n.sup.+ -layer is formed and a region in which it is not formed, and this leads to a serious problem.
Conventional memory cells use the side walls of a trench formed in an Si substrate as capacitors as disclosed in U.S. Pat. No. 4,397,075. A leakage current flows through adjacent capacitors and a minimum spacing between them is set in accordance with a structure or with an impurity concentration of the Si substrate. For these reasons, it has been difficult to fabricate a very small cell.
Japanese Pat. Laid-Open No. 137245/1983, which was invented by some of the co-inventors of the present invention, proposes a method of reducing this leakage current. However, this prior art technique employs a structure which can not be integrated easily in a high packing (integration) density environment.